This invention is in general related to simultaneous bidirectional data communication links, and in particular to techniques for subtracting an outbound wave from a transmission line signal and detecting simultaneously incoming data symbols.
I/O circuits act as the interface between different logic functional units of an electrical system. The functional units may be implemented in separate integrated circuit dies (i.e., IC chips) of the system. These chips may be in separate IC packages that have been soldered to a printed wiring board (i.e., PWB). The chips communicate with each other over one or more conductive transmission lines. The transmission lines may be a parallel bus formed on a PWB, and they may be of the point-to-point or multi-drop variety. Alternatively, the transmission line may be a serial link such as a coaxial cable. In both cases, each chip has an I/O circuit that includes a driver and a receiver for transmitting and detecting symbols. The driver and receiver translate between on-chip signaling and signaling that is suitable for high speed transmission (e.g., at several hundred megabits per second and higher) over a transmission line. In a ‘bidirectional link’, the driver and receiver pair are connected to the same transmission line.
In a simultaneous bidirectional (i.e., SBD) communication link, data symbols can be transmitted and received simultaneously over a single conductor of the transmission line, at each end of the communication link. Outgoing data symbols are encoded in an outbound wave that is transmitted by a driver over the transmission line, while incoming data symbols have been encoded in an inbound wave that is received over the transmission line. The transmission line signal, such as the voltage on the transmission line, is a superposition of the inbound and outbound waves. To detect a sequence of incoming data symbols, a copy of the outbound wave is subtracted from the transmission line signal to recover an estimate of the inbound wave. The incoming data symbols are then extracted or decoded from this estimated inbound wave in a subsequent comparison step, by repeatedly comparing the estimated inbound wave to one or more reference levels. These reference levels have been selected to discriminate between the different symbol levels. For example, to discriminate between two symbol levels which are ideally at 1.0 V and at 0.0 V, a reference level at 0.5 V may be used. This yields a margin of error of 0.5 V, which is the maximum allowed variation in the estimated inbound wave voltage (a variation greater than 0.5 V could yield an error in the detected symbol).
One of the difficulties in the SBD link described above is to how to generate an exact copy of the outbound wave, and then accurately subtract this from the transmission line signal. Part of the solution involves selecting the circuit that generates the copy of the outbound wave to be a replicate of the driver. This circuit is also referred to as a replica driver. The replica driver may, for example, include a 1:1 or scaled down structural duplicate of certain elements of the driver. However, in their manufactured versions, mismatch between corresponding circuit elements of the driver and its replicate is typically unavoidable. This mismatch renders a poorer or ‘noisy’ estimate of the inbound wave, which in turn reduces the margin of error allowed in the subsequent comparison step.